The output A2.7 is activated 2 seconds after opening input E1.5 for a period of 1 second.

The first line of the diagram below shows the development of the input, and the last line shows the output to be obtained. The second and third lines represent the development of the status of the two timers (T10 and T11) with an On-delay of 2 and 3 seconds and whose input signal is E1.5.
Note that the output Q0.7 should be true when the following conditions occur simultaneously: T11 true and T10 false. That is, in boolean terms: A2.7 = T11 · NOT(T10)

Time diagram of the delayed pulse

In the ladder program the first two paths are designed to activate the two timers. The input for both of them is the signal E1.5. The third path implements the recently obtained logical expression. The series of two contacts representing an AND and the use of an NC type for the second is the same as the negation of its operand.
In the same way, the first group of statements of the AWL program activates the two timers on receiving the input signal. The second group calculates the value of the boolean expression and assigns it to the output.

More examples: [ 1 ] [ 2 ] [ 3 ] [ 4 ] [ 5 ] [ 6 ] [ 7 ] [ 8 ] [ 9 ] [ 10 ] [ 11 ] [ 12 ] [ 13 ] [ 14 ] [ 15 ] [ 16 ] [ 17 ] [ 18 ] [ 19 ] [ 20 ] [ 21 ] [ 22 ] [ 23 ] [ 24 ] [ 25 ] [ 26 ] [ 27 ] [ 28 ] [ 29 ] [ List ]
More PLCs examples: Not still available